Exemplary embodiments of the present invention relate to a semiconductor design technology, and more particularly, to a semiconductor device having a clock delay correcting device which is capable of correcting a phase of a clock used to input and output data according to process, voltage and temperature (PVT) variations.
A system may use a plurality of semiconductor devices to store data. When a data processor, for example, a memory control unit (MCU), requests data, a semiconductor device may output data corresponding to an address inputted from the data processor, or store data provided from the data processor at a position corresponding to the address.
Recently, a high-speed memory device is often designed to input/output two-state data between a rising edge and a falling edge of a system clock applied from the outside, and input/output two-state data between a falling edge and a next rising edge of the system clock. That is, the memory device may be designed to input/output four-state data in one cycle of the system clock.
However, since the system clock has two states, that is, a logic high level and a logic low level, a data clock having two times the frequency of the system clock is required in order to input/output four-state data in one cycle of the system clock. That is, a clock dedicated to data input/output is required.
Therefore, a high-speed semiconductor device uses a system clock as a reference clock when transmitting/receiving an address and a command, and uses a data clock as a reference clock when inputting/outputting data. In this configuration, the data clock has two times frequency of the system clock.
That is, the data clock cycles through two cycles during one cycle of the system clock, and the data are inputted/outputted at a rising edge and a falling edge of the data clock. As such, four-state data are inputted/outputted in one cycle of the system clock.
A high-speed semiconductor device may input/output data by using two clocks having different frequencies for a read or write operation, respectively, as opposed to a conventional DDR synchronous memory device which uses one system clock for a read or write operation.
Here, if the phase of the system clock and the phase of the data clock are not aligned, the reference for transferring an operation command and an address and the reference for transferring a data may not align properly. This means that a high-speed semiconductor device may not operate normally.
Therefore, in order for a high-speed semiconductor device to operate normally, an interface training operation is desired to be performed between a semiconductor device and a data processor in an early stage of operation.
The interface training refers to an operation in which an interface for transferring a command, an address, and a data is trained to operate at an optimized/reasonable timing before a normal operation is performed between the semiconductor device and the data processor.
Such interface training includes an address training, a clock alignment training (WCK2CK training), a read training, and a write training. An operation of aligning a data clock and a system clock is performed in the clock alignment training (WCK2CK training).
FIG. 1 is a timing diagram illustrating a conventional write training operation.
Referring to FIG. 1, an internal data clock (WT SYNC. CLK) for a semiconductor device to receive a write data is a clock generated by compensating an external data clock (EXTERNAL WCLK) for an asynchronous delay of a path through which a clock is transferred inside the semiconductor device.
At this time, the asynchronous delay of the path through which the clock is transferred inside the semiconductor device and for which the external data clock is desired to be compensated, is a value which may vary depending on PVT variations. Therefore, the value may not be previously determinable, and thus may be determined through a write training operation.
After a semiconductor device is supplied with power and starts to operate, a semiconductor device controller (GPU) and a semiconductor device may perform a write training operation. The write training operation is an operation which finds an optimum/desirable write data input timing, at which a sufficient setup/hold time is ensured with reference to the internal data clock, by performing a time sweep (that is, performing tests at various timing points) of a write data with reference to the external data clock in the semiconductor device controller (GPU).
When the semiconductor device performs the write operation at the optimum/desirable write data input timing found through the write training at the early stage of operation, the semiconductor device controller (GPU) transfers the write data to the semiconductor device.
FIG. 2 is a timing diagram illustrating a conventional read training operation.
Referring to FIG. 2, an internal data clock (RD SYNC. CLK) for enabling a semiconductor device controller (GPU) to receive a read data from a semiconductor device is a clock generated by compensating an external data clock (EXTERNAL WCLK) for an asynchronous delay of a path through which a clock is transferred inside the semiconductor device.
At this time, the asynchronous delay of the path through which the clock is transferred inside the semiconductor device and for which the external data clock is desired to be compensated, is a value which may vary depending on PVT variations. Therefore, the value may not be previously determinable, and thus may be determined through a read training operation.
When a semiconductor device is supplied with power and starts to operate, a semiconductor device controller (GPU) and a semiconductor device may perform a read training operation. The read training operation is an operation which finds a timing position of a read strobe signal (GPU READ STROBE), where an optimum/desirable timing in a window period of the read data (data output valid window) can be determined with reference to the internal data clock (RD SYNC. CLK), by performing a time sweep of a read strobe signal (GPU READ STROBE) with reference to the external data clock (EXTERNAL WCLK).
After the semiconductor device performs the read operation for determining the position of the read strobe signal (GPU READ STROBE), at which the optimum/desired timing point in the window period of the read data (data output valid window) is found through the read training operation at the early stage of operation, the semiconductor device controller (GPU) determines the value of the read data transferred from the semiconductor device.
However, a considerable time is taken in completing the above-described write training operation and read training operation. Since the write training operation and the read training operation are performed at the early stage of operation of the semiconductor device, a great variation in an external voltage or an outside temperature during a prolonged operation of the semiconductor device varies a clock delay used to generate the previously determined optimum/desired read/write internal data clocks (RD/WT SYNC. CLK). Therefore, a sufficient setup/hold time may not be ensured at a window period of a write data, and an originally determined timing position of a strobe signal in a window period of a read data (data output valid window) may not be accurate.